Anoop Deekshith Ravikumar

RTL Design · Physical Design · Post-Silicon Validation

>Verilog · SystemVerilog · C++ · Neuromorphic

● READY | M.S. ECE @ UC Santa Cruz | San Francisco, CA

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Open for Roles &
Collaborations

Whether you're looking for an RTL engineer, a physical design collaborator, or someone who has lived in the post-silicon debug trenches — I'd love to hear from you.

⬡Full-time RTL / PD roles

⬢Research collaborations

◈Neuromorphic / edge AI projects

◇Post-silicon consulting

anoopdeekshith.ece@gmail.com

linkedin.com/in/anoopdeekshithr

github.com/AnoopDeekshith

medium.com/@anoopdeekshith

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// San Francisco, CA · Available for full-time roles and research collaborations
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Anoop Deekshith Ravikumar

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Open for Roles &Collaborations

Open for Roles &
Collaborations